1. Field of the Invention
This invention relates generally to the processing of signals in communication systems and, more particularly, to equalizer circuits. Equalizer circuits or adaptive filter units are used to compensate for distortion introduced into the channel during the transmission of signals. The present invention has particular applicability to modem units.
2. Description of the Prior Art
Referring to FIG. 1, a block diagram of a transceiver unit capable of advantageously using the present invention is shown. INPUT SIGNALS are applied to symbol encoder and side-stream scrambler unit 11. Output signals from the symbol encoder and side-stream scrambler unit 11 are applied to transmitter unit A 15 and to transmitter unit B 13. The output signals from transmitter unit A 15 are applied to hybrid unit 18, while the output signals from transmitter unit B 13 are applied to hybrid unit 17. The output signals from hybrid unit 17 and hybrid unit 18 are applied to cable 19. Signals from cable 19 are transmitted through hybrid unit 17 to receiver unit B 14 and through hybrid unit 18 to receiver unit A 16. The output signals from receiver unit A 16 and from receiver unit B 14 are applied symbol decoder and side-stream descrambler unit 12. The output signals from the symbol decoder and side-stream descrambler unit 12 are the OUTPUT SIGNALS from the transceiver.
In the transmitter unit A 15, the input signals are applied to a digital transmit filter unit 151. The output signals from the digital transmit filter unit 151 are processed by an digital-to-analog converter unit 152 and applied to an analog transmit filter unit 153. The output signal of the analog transmit unit 153 is the output signal of the transmitter A 15 which is applied to a hybrid unit 18. The transmitter B 13 is implemented in a similar manner.
With respect to the receiver A 16, the output signals from the hybrid unit 18 are applied to a VGA unit 169. The output signals from the VGA unit 169 are processed by an analog receive filter unit 168 and applied to an analog-to-digital converter unit 167. Output signals from the analog-to-digital converter unit 167 are applied to a digital linear forward equalizer unit 166 and to a gain, timing, control unit 170. The signals from the digital linear forward equalizer unit 166 are applied to a summation network 165 and to the gain, timing and control unit 170. The gain, timing and control unit 170 applies control signals to the VGA unit 169 and to the analog-to-digital converter unit 167. The summation unit 165 also receives signals from an echocanceller unit 161, from a NEXT canceller unit 162 and from a feedback filter/noise predictor unit 164. Output signals from the summation unit 165 are applied to a decision unit 163. The decision unit 163 provides the output signal for receiver A 16. The output signal from the decision unit 163 is also applied to the feedback filter/noise prediction unit 164. The decision unit 163 applies an error signal to the echo canceller unit 161, to NEXT canceller unit 162, to feedback filter/noise reduction unit 164, and digital linear forward equalizer unit 166. The echo canceller unit also receives signals which are applied to the transmitter A 15 associated with the receiver A 16, while the NEXT canceller unit 162 receives an input signal from the transmitter B 13 not associated with the receiver unit A 16 which includes the NEXT canceller unit 162. The receiver B 13 is implemented in a manner similar to receiver A 16.
Referring to FIG. 2, a block diagram of an adaptive equalizer filter unit 20, such as would be used to implement the echo canceller unit 161 and the NEXT canceller unit 162 of FIG. 1, is shown. The equalizer unit 20 includes a multiplicity N of stages. Each stage n of the equalizer unit 13 includes a delay line Dn, (the delay line D0 is shown with dotted lines because the presence of this delay line is not needed to the operation of filter 20. The delay lines D0-DNxe2x88x921 of all of the stages are coupled in series. The output terminal of each delay line Dn is coupled, in addition to being coupled to the next sequential delay line Dn+1, to a multiplier unit Mn associated with the nth stage and to an input terminal of update unit Un associated with the nth stage. Each multiplier unit Mn also receives a coefficient signal Cn. The coefficient signal Cn is a signal group stored in the update unit Un which is updated Un in response to an ERROR signal e and the output signal of delay line Dn. An ERROR signal e is generated as a result of each signal group processed in the decision unit shown in FIG. 1. The product of the signals Cn and the output signal from delay line Dn formed in multiplier unit Mn is applied to one terminal of adder unit Am. The adder unit Am also receives an output signal from one of the neighboring filter stages. The adder units A0-AMxe2x88x921 are the first stage of an adder tree, the remaining adder units would be included in element 29. The output signals of the adder tree, including the adder units A0-AMxe2x88x921 and the element 29, are the DATA OUT signals (Xxe2x80x2).
The signals applied to the multiplier unit Mn are the following:
Xn is the output signal from delay line Dn, and
Cn,t+1 is given by the formula Cn,t+1=Cn,t+xcexcetXn,txe2x88x921 
The error signal is implemented with a plurality of digital bits. In the implementation of the transceiver of the present invention, 8 bits, including a sign bit, are used to represent the error signal. This error signal is generated in the two""s complement format to expedite selected processing procedures. None-the-less, because the error signal, as described in the foregoing equations, is used in a multiplication procedure, a large portion of the components of the transceiver can be devoted to the multiplication.
A need has therefore been felt for apparatus and an associated method to reduce the number of components required to implement a transceiver unit, and more particularly, to reduce the number of components in (while increasing the throughput of) the transceiver unit dedicated to processing the error signal in the adaptive filter unit.
The aforementioned and other features are accomplished, according to the present invention, by providing apparatus for reducing a plurality of the most significant bits to a single bit in an adaptive filter error signal, the error signal being implemented in a two""s complement format. This single bit composite most significant bit, the sign bit, and the remaining bits of lesser significance are applied to the adaptive filter. Because the number of bits representing the error signal has been compressed (i.e., reduced), both the amount of apparatus required to process the error signal in the adaptive filter unit, as well as the time required in the processing of the error signal is reduced. The time for the convergence of the error signal to a steady state value is increased as a result of the compressed representation of the error signal.
These and other features of the present invention will be understood upon the reading of the following description in conjunction with the Figures.